module register_file (
    input           clk,
    input   [4:0]   A1,
    input   [4:0]   A2,
    input   [4:0]   A3,
    input   [31:0]  WD3,
    input           WE3,

    output  [31:0]  RD1,
    output  [31:0]  RD2
);

reg [31:0] reg_file [31:0];  //32个寄存器

always @(posedge clk) begin
    if(WE3 && A3!=5'b0)
        reg_file[A3] <= WD3;
end

assign RD1 = (A1==5'b0) ? 32'b0 : reg_file[A1];
assign RD2 = (A2==5'b0) ? 32'b0 : reg_file[A2];
    
endmodule
